The present invention relates to a vertical field effect transistor having a protrusion formed on a substrate, wherein the side wall of the protrusion is used as a channel region and to a method for manufacturing the transistor.
In recent years, a semiconductor device constituting a MOS transistor has been widely studied in which a groove is formed on a silicon substrate and the side walls of the groove are used as a channel region in order to improve the scale of integration of the semiconductor device.
A configuration of such a semiconductor device, i.e., what is called a vertical MOS transistor, is shown in FIG. 1. This vertical MOS transistor 41 comprises a semiconductor substrate 42 made of a p-type silicon formed with a groove which forms a recess 42a and a protrusion 42b on the semiconductor substrate 42.
On the surface of the recess 42a of the semiconductor substrate 42 there are formed, from the surface side down, an n-type high-concentration region (n+) 43a and an n-type low-concentration region (n-) 43b. Both the regions 43a and 43b make up an n-type source region 43. On the surface of the protrusion 42b of the substrate 42 there are formed, from the surface side down, an n-type high-concentration region (n+) 44a and an n-type low-concentration region (n-) 44b. Both the regions 44a and 44b constitute an n-type drain region 44.
A gate insulating film 45 made of an oxide film or the like is formed on the semiconductor substrate 42.
On each side wall of the protrusion 42b of the semiconductor substrate 42 there is formed with a gate electrode 46 made of polysilicon or the like through the gate insulating film 45.
An inter-layer insulating layer 47 is formed over the entire surface of the elements mentioned above, and an opening is formed through the inter-layer insulating layer 47 and the gate insulating film 45 above the high-concentration region 44a of each drain region 44. A plug contact 48 made of tungsten or the like, for example, is formed in each opening.
Further, a metal wire 49 made of Al or the like is formed on each plug contact 48 to lead an electrode from the drain region 44.
In this vertical MOS transistor 41 of a LDD (lightly doped drain) type, a channel region is formed in the side wall portion of the protrusion 42b opposing to the gate electrode 46 through the gate insulating film 45, i.e., between the source region 43 and the drain region 44.
With the configuration of FIG. 1, a distance between the drain region 44 and the source region 43, i.e., a channel length (gate length) L is determined by the depth of the groove formed on the semiconductor substrate 42. However, if the depth of the groove is scattered from one groove to another, the channel length L is scattered and hence the characteristic of the MOS transistor is also varied, thereby making it impossible to secure stable characteristics of a semiconductor device as a whole.
The depth of the groove develops some degree of variations during the manufacturing process, sometimes resulting in unstable characteristics.